Samsung gave the first detailed look at its long-awaited 7nm process at the VLSI Symposia in Honolulu this week. The talk was especially newsworthy because Samsung is likely to be the first to introduce a new form of lithography, known as EUV because it uses extreme ultra-violet light, that has been in development for some 30 years.
Chipmakers currently rely on lithography tools from ASML or Nikon with an argon fluoride (ArF) excimer laser that produces deep ultra-violet light with a wavelength of 193nm. These scanners also use a technique called immersion lithography to enhance the resolution, but they still can’t pattern critical features at the most advanced nodes without complex and costly multi-patterning steps. The introduction of ASML’s EUV lithography, which uses a completely different laser-produced plasma to generate 13.5nm light, provides several potential advantages.
First, it enables accurate patterning of much smaller features to extend scaling. Samsung’s 7nm process has a 27nm fin pitch and a 54nm gate pitch, which results in the smallest FinFET transistors reported to date. It also has the smallest high-density SRAM cell size at 0.0262 square microns. The overall result is a 40 percent shrink in comparison with its current 10nm process used to manufacture Qualcomm’s Snapdragon 845 and Samsung’s own Exynos 9810.
Second, the use of EUV results in better pattern fidelity and less variability at these dimensions. in other words, what you print, is what you get. Samsung emphasized that the 70 percent better pattern fidelity versus current 193nm ArF immersion scanner with multi-patterning provides a big advantage when ramping advanced logic to manufacturable yields.
But perhaps most important, EUV should reduce overall cycle time and cut costs. By using EUV at 7nm, Samsung can fabricate contacts and some metal layers with a single step rather than using 193nm ArFi with multiple exposures. Samsung has previously said this will reduce mask steps by at least 25 percent and in this week’s presentation, it said its 7nm technology with EUV will revive the “cost-effectiveness of cutting-edge technolgy.” But this cost advantage may hinge on a number of factors including the development of a better EUV pellicles to protect masks from contamination, the dose required to avoid random defects (the higher the dose, the longer the cycle time), and new inspection tools to find and repair tiny defects.
Samsung produced 256Mb high-density SRAM test chips using the 7nm platform and achieved yields of more than 50% with good operation. The company also produced a 7nm application processor with a quad-core CPU, six-core GPU and SRAM caches that was fully operational. The 7nm EUV technolgy will deliver 20-30 percent higher transistor performance and use 30-50% lower power–an improvement over the early 7nm EUV test results that Samsung presented at last year’s conference in Kyoto.
At its annual Foundry Forum last month, Samsung said it was on track to start risk production of 7nm later this year. It can take up to one year to transition from risk production to full volume production, and Samsung also said that some of the IP blocks won’t be available until the first half of 2019, so it seems unlikely that 7nm will be ready in time to produce application processors for the Samsung Galaxy S10 next spring. As a stopgap, Samsung has developed an 8nm process, which it will present in a talk tomorrow that will be followed by a Qualcomm presentation on a 10nm Snapdragon SoC that can be extended to the 8nm technology.
Rival TSMC, the world’s largest contract chipmaker, has chosen a different strategy, sacrificing some shrink to get 7nm to market faster using current lithography tools. Its first 7nm process, CLN7FF, is already in volume production and TSMC says it has more than a dozen customers and expects to tapeout more than 50 designs by the end of the year for a variety of chips including mobile application processors, server CPUs, graphics processors, FPGAs, network processors and AI accelerators. One of those is rumored to be Apple’s A12 processor for the next family of iPhones.
TSMC has not been as forthcoming with its 7nm features, though we do know that the high-density SRAM cell measure 0.027 square microns. Since 10nm was a “short-lived node,” TSMC likes to compare CLN7FF with its 16nm technology (CLN16FF+) where it promises a 70% shrink, and either a 30% boost in performace or a 60% reduction in power. Next year, TSMC plans to roll out an enhanced 7nm processor (CLN7FF+) using EUV for some steps–most likely contacts and vias–that will provide an additional 20% shrink and use 10% less power.
GlobalFoundries has a similar strategy but it is further behind. At IEDM late last year, the foundry announced its first 7nm process, using ArFi with quadruple patterning, which should soon be in risk production and will be in mass production sometime in 2019. This 7LP process will be used to manufacture AMD and IBM processors–among other chips–though it is worth noting that AMD recently revealed that its first 7nm Radeon GPUs due out later this year will actually be fabricated by TSMC.
The 7LP process has a fin pitch of 30nm and gate pitch of 56nm, and the SRAM cell size measures 0.0269 square microns. Overall GlobalFoundries promises 40 percent better transistor performance (or 55 percent lower power) and a 30 percent cost reduction. A high-performance version will deliver an additional 10 percent speed boost. Note that GlobalFoundries is comparing 7LP to its current 14nm process (licensed from Samsung) because it skipped 10nm altogether, though it will give a talk on its interim 12nm process at VLSI this week. The 7LP process will be followed by versions that use EUV for contacts and vias, and eventually some metal layers.
Intel is still wrestling with yields for its 10nm technology and now expects to start production of mainstream processors sometime in 2019. The node names are misleading and Intel’s 10nm process, which uses ArF immersion with self-aligned quadruple patterning, is similar to the foundries’ 7nm nodes. The 10nm process has a fin pitch of 34nm and gate pitch of 54nm, and a SRAM cell size of 0.0312 square microns. Intel is also working on EUV but has not said when it will introduce it in volume manufacturing.